?????Homework 5 Given a processor implemented by a single-cycle control and datapath shown in Figure 1. Assume that the functional blocks adopted to implement the datapath have the following latencies in Table 1, and we need to design a processor that can support the MIPS instructions listed in Table 2: regster 2 Figure 1. The single-cycle datapath with the control unit Table 1. Latencies of the functional units on the datapath PCs Ctri ALU Regs Data- Sign- AND-Shift- Unit Ctri. Access Mem. extend Gate left-2 Inst. CIk- Add Mux ALU Mem. Ops | 600ps | 200ps | 50ps | 250ps | 150ps | 50ps | 300ps | ps | 100ps | 50ps | Mp Table 2. MIPS Instruction Opcode & Funct fields Opcode Funct Instr add 32 34