Question: implement a decoder with verilog and VHDL, and simulate them respectively and print out the waveforms. Please provide waveforms for both simulations Hibrary IEEE; use

implement a decoder with verilog and VHDL, and simulate them respectively and print out the waveforms. Please provide waveforms for both simulations

print out the waveforms. Please provide waveforms for both simulations Hibrary IEEE;

Hibrary IEEE; use IEEE.std_logic_1164.s11; use IEEE,std_logic_arith. sl1; entity DECOoER_TB is entity declarstion end DECOOER_TB; architecture TB of DECOoER_TB Is begin \[ \text { U_DECOOER: DECOOER port mop }\left(T_{-} I, T_{-} 0 ight) \text { : } \] process .. variable should be declared within process voriable err_cht : integer : e e; begin sever1ty error; If (To/eeen )) then end if; " case "e1" wait for 10ns; T_I - "e1"; wait for 1 ns: assert (T_o-"e1e") report "Error Case 1" severity error: If (T_o/ ="001e") then err_ent : err_cnt +1; end 1f: * sumary of s11 the tests If (err_cnt=e) then assert folse report "Testbench of Adder completed successfully!" severity note; else assert true report "Something wrong, try again" severity error; end if; wait; end process: end TB; configuretion CFO_TB of otcooth_TB is for T6 end for: end CFG_TB

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