Implement and verify a digital system which will enable a pulse the period (50us) of the

Implement and verify a digital system which will enable a pulse ½ the period (50us) of the clock signal to be selected every 5 clock periods (500us) or every 10 clock periods (1ms) depending on the setting of a single input. how can you produce a pulse ½ period of the clock. The implementation should be a synchronous sequential circuit and not make use of clear or preset controls on the flip-flops. You may assume that you have a 10 Khz clock signal that can be used as the clock input to the pulse generator. 

• Investigate and explain the delays in the circuit. i.e. what happens after the clock edge? 

• Using the information about the delays, determine the (approx.) maximum clock speed of the systems.

Answer rating: 100% (QA)

CPU 8085 TBL Processor declaration ORG 2000n user code starting address LXI SP ... View the full answer