Implement the ALU shown in Figure 1 using Verilog, the ALU must be implemented using structural models only, and should meet the following requirements. Register File Reg A Reg B Regc Reg D Opi Sel Opi Op2 Op2 Sel Operation ALU Result Status Figure 1. ALU model There is a control line named operation Operation is responsible for selecting the operation to be performed by the ALU The ALU has two 8-bit input Ports (Op1 and Op2). Opi and Op2 values are fetched from the registers (A, B, C and D) based on Op1 Sel and Op2 Sel control lines. As shown in Table 1. 1 Operand Selection 00 01 10 11 Selected Register B D Table 1. Register Select The ALU has two output registers: result and status. Result is an 8-bit register while status is a 3- bit register. The operations being performed in the ALU are based on table 2. Operation ALU operation Result register Status Register affected bits 0000 0001 0010 0011 0100 ZC ZV 0101 0110 NN One's complement for Op1 One's complement for Op1 Two's complement for Op1 Two's complement for Op1 Addition Op1 + Op2 Subtraction Op1 - Op2 Comparator O{if Op1 > Op2) 1{if Op1 = Op2) 2{if Opi Op2) 1{if Op1 = Op2) 2{if Opi