Question: In a 5-stage pipelined CPU without any structural, data and control hazards assume the following table for a specific program. a. (7pts) Assume if there

In a 5-stage pipelined CPU without any structural, data and control

In a 5-stage pipelined CPU without any structural, data and control hazards assume the following table for a specific program. a. (7pts) Assume if there is no cache miss the memory stage needs only one cycle. If there was no data or instruction cache miss, what would be the total execution time of this program in seconds? b. (18pts) Assume the miss rates and miss penalties given in the above table then what would be the total execution time in seconds? Show your computations clearly

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