In a pipelined MIPS implementation, what is done when an arithmetic overflow exception is detected?

$q,$

The pipeline is paused until the exception is cleared.

The pipeline stages following the exception are flushed, and control is transferred to the exception handler.

The exception is ignored until the current instruction batch completes.

The result of the overflow is corrected automatically by the hardware.

Question $44$

$2$ pts

What is the significance of a "pipelined" MIPS implementation?

It refers to a technique for increasing computational speed by performing multiple operations simultaneously.

It simplifies the instruction set architecture.

It involves constructing a more realistic processor capable of faster and more complex operations.

It is a simplified version of processor implementation used for educational purposes.