In class, we discussed a processor that takes $800$ ps for a clock cycle. When $5-$stage pipelined, the processor required $200$ ps for a clock cycle. How much was the slowdown in latency, and why did it happen?

$($Hint: not every sub$-$step needed $200$ ps$,$ register read$/$write needed $100,$ but all steps were made the same length to fit. Flesh out the details.$)$

Despite the increased latency, the pipeline executes a long sequence of instructions faster than the single$-$cycle design. Explain why, and how much speedup we get in the ideal case. Given $20\%1-$cycle instructions, $25\%2-$cycle, $30\%3-$cycle, $5\%4-$cycle, and $20\%5-$cycle. What is the average CPI, and how fast $($in million instructions per second$)$ will the processor run this program? Answer for both the single$-$cycle and the pipelined version.