In this lab, you are given an arithmetic logic unit $($ALU$)$ design, which you are to test. The design has

some bugs in it$.$ You will design a testbench to test the functions of the ALU to find the bugs. You will

also revise the sequential logic $($D flip$-$flops$)$ and create testbench for it$.$

$1$ ALU Overview

An ALU performs basic arithmetic and logic operations. Examples of arithmetic operations are addition,

subtraction, multiplication, and division. Examples of logic operations are comparisons of values $,$such

as NOT, AND, and OR$.$ This ALU has $24-$bit inputs A and B for operands, a $4-$bit input ALU Sel for

selecting the operation, a $4-$bit output ALU Out, and a $1-$bit output CarryOut. The datapath is just

$4-$bits wide to allow for easy coverage testing of the different operations. The operations of the ALU are

specified in the table below.

ALU Sel ALU Operation

$0000$ ALU Out $=$ A $+$ B

$0001$ ALU Out $=$ A $-$ B

$0010$ ALU Out $=$ A $*$ B

$0011$ ALU Out $=$ A $/$ B

$0100$ ALU Out $=$ A $<<1$

$0101$ ALU Out $=$ A $>>1$

$0110$ ALU Out $=$ A rotated left by $1$

$0111$ ALU Out $=$ A rotated right by $1$

$1000$ ALU Out $=$ A and B

$1001$ ALU Out $=$ A or B

$1010$ ALU Out $=$ A xor B

$1011$ ALU Out $=$ A nor B

$1100$ ALU Out $=$ A nand B

$1101$ ALU Out $=$ A xnor B

$1110$ ALU Out $=1$ if A$>$B else $0$

$1111$ ALU Out $=1$ if A$=$B else $0$

Note: Check canvas for some review slides on Verilog operators.

$1$