Assume that the logic blocks used to implement a processor's datapath have the following latencies $($all the units are ps$)$:

I$-$Mem$/$D$-$Mem Register PC Mux ALU Adder Gate Sign Ext Shift Left $2$ Control ALU Ctrl

$2501005025220110555204550$The datapath is redesigned to support pipelining as shown in the diagram below, with the latency of each pipeline register as $105$ ps$.$

What is the cycle time for the single$-$cycle design?

In the pipelined design, what is the latency of the IF stage?

In the pipelined design, what is the latency of the EX stage?

In the pipelined design, what is the latency of the MEM stage?

What is the cycle time for the pipelined design?

How many picoseconds does it take to execute $80$ instructions with the single$-$cycle design?

How many picoseconds does it take to execute $80$ instructions with the pipelined design?

What is the speedup of the pipelined design compared to the single$-$cycle design for $80$ instructions?

What is the speedup of the pipelined design compared to the single$-$cycle design for endless instructions? Round it to the nearest hundredth.

Enter the answers separated by commas, for example, $"1,2,3,4,5,6,7,8\mathrm{.}00,9\mathrm{.}00"($without the quotes$).$

Your Answer: give up

Correct Answer: $1020,405,480,460,480,81600,40320,2\mathrm{.}02,2\mathrm{.}12$

Your score is $0\mathrm{.}00$ out of $10.$