Question: In Verilog, a memory with 4 - bit address lines and 8 - bit data lines can be declared: reg [ 7 : 0 ]

In Verilog, a memory with 4-bit address lines and 8-bit data lines can be declared:
reg[7:0] memory 3:0;
In Verilog, a memory with 4-bit address lines and 8-bit data

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