In VHDL$,$ implement the following asynchronous counter $($not Synchronous$)$ using the following TFlipFlop program as a source code. Include a testbench.

entity tFF is

$--$ Port $()$;

Port $($ Rin, Sin, Tin, CK: in std$\_$logic;

Qo : inout std$\_$logic$)$;

end tFF;

architecture TFF of tFF is

begin

process $($CK$)$

begin

if $(($ CK'event and CK $=\text{'}1\text{'})$ and $(($Rin $=\text{'}1\text{'})$ and $($Sin $=\text{'}1\text{'})))$ then

if $($Tin $=\text{'}0\text{'})$ then

Qo Qo;

elsif $($Tin $=\text{'}1\text{'})$ then

Qo not Qo;

end if;

end if;

if $($Rin $=\text{'}0\text{'})$ then

Qo ;

elsif $($Sin $=\text{'}0\text{'})$ then

Qo ;

end if;

end process;

end designTff