Initialize the first 10 words of the Data memory with the following HEX values: 00000AA 10000011 20000022 30000033 40000044 50000055 60000066 70000077 80000088 90000099 Write a Verilog code that implement the following instructions using the design shown in Figure 2 and Figure 3. Write a Verilog test bench to verify your code: (You have to show all the signals written into the IF/ID register and the ID/EXE register in your simulation outputs address instruction Comment $2 memory [$1+001 load x 100: lw $v0, 00 ($at [0 3 memory [$1+041 load x [1] 104 lw $v1, 04 (Sat Assume that the register $at has the value of 0