$)$ Instruction execution time for a processor is $2$ cycles and provides an on$-$chip cache with access time of $1$ cycle. Each instruction requires, on average, $1$ memory access for the instruction and $2$ accesses for data. The internal cache is implemented as a Harvard cache $($separate I cache and D cache$).$ The processor can overlap instruction execution with access to the internal $($L$1)$ cache. The hit ratio to the L$1$ instruction cache is $92\%,$ and the hit ratio to the L$1$ data cache is $87\%.$ A unified external $($L$2)$ cache requires $6$ cycles to access and has a global hit ratio of $98\%.$ The main memory requires $25$ cycles to access. What is the average MIPS rate of the processor if it is clocked at $400$ MHz$?$