Latencies beyond single cycle

What is the baseline performance $($in cycles, per loop iteration$)$ of the code sequence

given above if no new instruction's execution could be initiated until the previous

instruction's execution had completed? Ignore front$-$end fetch and decode. Assume for

now that execution does not stall for lack of the next instruction, but only one instruction$/$

cycle can be issued. Assume the branch is taken, and that there is a one$-$cycle branch

delay slot.