Question: Let TS be the average time to access an item in memory. Let T1 be the time to access an item in level 1 cache

Let TS be the average time to access an item in memory.

Let T1 be the time to access an item in level 1 cache

Let T2 be the time to access an item in level 2 cache

Let TM be the time to access an item in main memory

Let H1 be the hit rate for level 1 cache.

Let M2 be the miss rate for level 2 cache.

Also consider that the average memory access time per instruction is AMAT = Time for a hit x Miss rate x Miss penalty

e. If the system in (d) misses 2.5% of the time, whats the new effective CPI with one level of cache? Use the equation Total CPI = Base CPI + Memory-stall cycles per instruction Total CPI = _________________________________________ cycles per instruction. # of clocks for a main memory access 400. Assume you have a 4 GHz CPU with a CPI of 1.0 (instructions on this CPU require 1.0 cycles per instruction on average) and a main memory access time of 100 ns

What is the total access time for an access that is a miss in L1 and L2 but a hit in main memory? Expand the Total CPI equation from (e) above to add memory stalls for L2.

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