Let us consider a computer with a L1, L2 and L3 cache memory hierarchy with the following parameters: Processor Clock Frequency = 1 GHz ;

Hit Time L1 = 1 clock cycle ; Hit Rate L1 = 95%;

Hit Time L2 = 4 clock cycles; Hit Rate L2 = 92% ;

Hit Time L3 = 8 clock cycles; Hit Rate L3 = 90% ; Miss Penalty L3 = 15 clock cycles;

Given Memory Accesses Per Instruction = 78% ; CPI exec = 3, how much is the impact on CPU time of the L1 and L2 cache when considering an IDEAL L3 cache ?

IDEAL L3 cache means Hit Rate L3 = 100%