Modify the single-cycle ARM processor to implement one of the following instructions. Refer to the ARM instructions document for a definition of the instructions. Mark up a copy of Figure 1 to indicate the changes to the datapath. Name any new control signals. Mark up a copy of Table 1 and Table 2 to show the changes to the Main Decoder and ALU Decoder. Describe any other changes that are required 1. (a) TST (b) LSL (c) ADC (ADD Carry) PCSrc ontrol Unit MemtoR 31 28 2726 520 Funct 1512 Rd Cond MemWrite ALUControl ALUSrc ImmSrc RegWrite Flags ALUFlags CLK CLK CLK 19.16 SrcA WE PCPC A1 RD1 A RD Instruction Memory 15-1 3.0 ALUResult ReadData A RD Data Memory RA2 A2 RD2 15:12 WriteData A3 Register WD3 File 4 PCPlus8R15 PCPlus4 23.0 Extend Extlmm Result Figure 1. Complete Single-cycle processor Modify the single-cycle ARM processor to implement one of the following instructions. Refer to the ARM instructions document for a definition of the instructions. Mark up a copy of Figure 1 to indicate the changes to the datapath. Name any new control signals. Mark up a copy of Table 1 and Table 2 to show the changes to the Main Decoder and ALU Decoder. Describe any other changes that are required 1. (a) TST (b) LSL (c) ADC (ADD Carry) PCSrc ontrol Unit MemtoR 31 28 2726 520 Funct 1512 Rd Cond MemWrite ALUControl ALUSrc ImmSrc RegWrite Flags ALUFlags CLK CLK CLK 19.16 SrcA WE PCPC A1 RD1 A RD Instruction Memory 15-1 3.0 ALUResult ReadData A RD Data Memory RA2 A2 RD2 15:12 WriteData A3 Register WD3 File 4 PCPlus8R15 PCPlus4 23.0 Extend Extlmm Result Figure 1. Complete Single-cycle processor