Question: module DU _ 2 ( clk , rst , a , b , c , d , e , sel 1 , sel 2 ,
module DUclk rst a b c d e sel sel sel sel self, sel selml,
input :;
input clk;
input : se;
input sel se sel sel sel selm selm;
output : R R R R mulout, addout;
reg: mulout, addout:
reg : sr;
Max
alwayse sel mulout, addout, a
gcase sel
:;
: sx addout;
defaule: thes?
endicase
alwayse sel c add out
if seliz
sradd out:
else
;
misk
alwayse se b add out
if sel
s add out :
else
:
mux
alwaysse en dy
elise
Step by Step Solution
There are 3 Steps involved in it
1 Expert Approved Answer
Step: 1 Unlock
Question Has Been Solved by an Expert!
Get step-by-step solutions from verified subject matter experts
Step: 2 Unlock
Step: 3 Unlock
