More Virtual Memory Consider a processor with a TLB access time of 7ns, an L1 access time of 10ns, an L2 access time of 50ns, and a memory access time of 2 us. Consider also that a TLB miss, which requires a page walk (the process of looking through pages in memory and finding the desired page-frame mapping), takes 20 us. a) What is the total access time of a memory address if it is absent from L1 but present in L2 and the TLB. Consider L1 to be virtually addressed but L2 to be physically addressed (physically tagged and physically indexed) b) What is the total access time of memory address if it is absent from the TLB but present in both LI and L2. Consider L1 and L2 to both be physically tagged and virtually indexed. c) What is the total time needed for a memory access for data that is in neither cache but who's reference is in the TLB. Consider that L1 and L2 are both physically tagged and physically indexed