Multi$-$cycle processor design $($assume the design in our class$)$: Assume the

control signal values for ALUOp: $00$ for subtraction, $01$ for addition, and

$10$ for $"$fc dependent". What are the values of all control signals for a

specific stage $($clock cycle$)$ of the instruction $sw?$ Give your answer with

the sequence: PCWriteCond, PCWrite, IorD, ALUSrcA, ALUSrcB,

ALUOp, PCSource, MemRead, MemWrite, MemtoReg, IRWrite, RegDst,

RegWrite. If the value of a control signal is "don't care", give $"x".$

$($a$)[8\%]{33}^{rd}$ stage

$($b$)[8\%]4^{th}$ stage