Multi$-$cycle Processor

Multi$-$cycle processor design $($assume the design in our class$)$: Assume the

control signal values for ALUOp: $11$ for subtraction, $01$ for addition, and

$00$ for $$fc dependent$.$ What are the values of all control signals for a

specific stage $($clock cycle$)$ of the instruction slt $($set on less than$)?$ Give

your answer with the sequence: PCWriteCond, PCWrite, IorD, IRWrite,

RegDst, RegWrite, ALUSrcA, ALUSrcB, ALUOp, PCSource, MemRead,

MemWrite, MemtoReg. If the value of a control signal is $$don$$t care$,$ give

$$x$$

$.$

$($a$)[8\%]2$nd stage

$($b$)[8\%]4$th stage