My vhdl code is giving me errors in my architecture behavioral can someone please fix these for me

library ese- use IEEE.STD LOGIC 1164.all: uge entity alu32 is portf : in STD LOGIC VECTOR (31 dounts 0) a, b ALUConEx8l in STD LOGIC VECTORii demteR 0) Result ALUFlags,out STD LoGIC VECTORI3 desnE 0) : buffer STD LOGIC ECTOR(31 denER 0)F end alu32; architecture behavioral of alu32 is signal condinzb: STD LOGIC VECTOR (31 demto. o)i signal sum: STD LOGIC VECTOR 132 dents 0)F signal neg, zero, carry, overfloW: STD LOGIC; begin begin sondinER result result re gult ( thers => '-'); end case: end precess: neg = 1; zero