N-bit Multiplier VHDL code

I need to finish the testbench without changing any of the given code.

- -Behaviour Modeling of N-bitN-bit Multiplier library ieee; use ieee.std logic 1164.all; use 1eee.std logic unsigned.alL entity NMult is port (Clr,cik: in std logic; A,B: in std logic vector; R: out std logic vector) end NMult; architecture Behave of NMult is begin Multiply: process (Clk, Clr) subtype Rs is natural range (2 A'Length) -1 downto 0; variable Tm: std logic vector (Rs): begin if Clr1then Tm := (others => R