Need help with this thanks!

heres the table it comes with

Question 2. Suppose that we modified the pipelined MIPS architecture described in Question 1 such that all data memory reads and memory writes were split into two separate stages of 150 ps each. a) Would the overall throughput increase or decrease in the modified architecture? Why? [15 Points] b) What would the resulting speedup be? [5 Points] Question 1. Assume that the MIPS stages have these latencies (in ps): Instruction Register Execute Data Register Memory Read Memory Write 200 100 100 250 150 What is the clock vele time for a nonninelined processor? [5 Points