Question: o) Write structural Verilog code for full adder circuit and verify the results. Use basic gates (AND, OR, NOT) to implement the full adder circuit

o) Write structural Verilog code for full adder circuit and verify

o) Write structural Verilog code for full adder circuit and verify the results. Use basic gates (AND, OR, NOT) to implement the full adder circuit and don't use XOR gates. The report should contain Aim, Truth table, Boolean expression, Verilog code, Simulation results for different combinations of inputs (as per in the truth table) and inference

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