Objectives. Learn how data cache reduces memory access time for read$/$write memory references.

For the $1-$way set associative $($direct mapped$)$ data cache with $16$ cache sets, $2$ words $(8$ bytes$)$ per block, and LRU cache replacement policy and write$-$allocate and write$-$back policy, simulate the data cache with the provided memory reference trace. $[20$points$]$

$\backslash$table$[[$R$/$W$,\backslash$table$[[$Memory$],[$Address$]],$Tag,Index,Offset,Result,Memref$],[$W$,04d4,,,,,],[$W$,011d0,,,,,],[$R$,04d8,,,,,],[$R$,04dc,,,,,],[$W$,011d4,,,,,],[$R$,04d4,,,,,]]$

For the $1-$way set associative $($direct mapped$)$ data cache with $8$ cache sets, $4$ words $(16$ bytes$)$ per block, and LRU cache replacement policy and write$-$allocate and write$-$back policy, simulate the data cache with the provided memory reference trace. $[20$points$]$

$\backslash$table$[[$R$/$W$,\backslash$table$[[$Memory$],[$Address$]],$Tag,Index,Offset,Result,Memref$],[$W$,04d4,,,,,],[$W$,011d0,,,,,],[$R$,04d8,,,,,],[$R$,04dc,,,,,],[$W$,011d4,,,,,],[$R$,04d4,,,,,]]$