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3. Figure 1 shows the datapath and control unit of a MIPS pipelined processor with data forwarding capability. Please write down the control signals for the following code sequence at different clock cycles. You are required to specify don't care condition if any. (10%) Instruction1: sw $0,50($1) Instruction2: lw $5,70($2) Instruction3: sub $3, $2, $4 Instruction 4: and $3, $3, $6 Instruction5:or $0, $7,$3 Instruction 6: xor $7, $3, $0 Instruction 7: add $5, $4, $3 5th cycle 6th cycle 7 cycle gth cycle 9th cycle RegDst ForwardA ForwardB MemtoReg RegWrite MemRead Mem Write 3. Figure 1 shows the datapath and control unit of a MIPS pipelined processor with data forwarding capability. Please write down the control signals for the following code sequence at different clock cycles. You are required to specify don't care condition if any. (10%) Instruction1: SW $0,50($1) Instruction2: lw $5,70($2) Instruction3: sub $3, $2, $4 Instruction4: and $3, $3, $6 Instruction5:or $0, $7, $3 Instruction 6: xor $7,$3, $0 Instruction7: add $5, $4, $3 5th cycle 6th cycle 7 cycle gth cycle gih cycle RegDst ForwardA ForwardB MemtoReg RegWrite MemRead Mem Write