On Architecture A$,$ how many clock cycles does it take until the last MUL instruction reaches the $W$ stage?

mul.D F$2,$ F$3,$ F$4$

mul.D F$5,$ F$6,$ F$7$

mul.D F$8,$ F$9,$ F$10$

$\backslash$table$[[,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,],[,,,,,,,,,,,,,,,,],[,,,,,,,,,,,,,,,,],[,,,,,,,,,,,,,,,,],[,,,,,,,,,,,,,,,,]]$

On Architecture A$,$ how many clock cycles does it take until the last DIV instruction reaches the W stage? Mark cycles dedicated to division with $\text{'}V\text{'}.$

div.D F$2,$ F$3,$ F$4$

div.D F$5,$ F$6,$ F$7$

$\backslash$table$[[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21],[,,,,,,,,,,,,,,,,,,,,],[,,,,,,,,,,,,,,,,,,,,],[,,,,,,,,,,,,,,,,,,,,]]$