P2 (8 points): Derive a minimal state table for a Moore FSM that acts as a three-bit parity generator. For every three bits that are observed on the input b during three consecutive clock cycles, the FSM generates the parity bit p-1 if and only if the number of 1s in the three-bit sequence is even. Note that the output p may only assert after a set of three bits (six, nine, twelve, etc.) have been input. The FSM will initially have no bits and must output a 0. From this point (or any point immediately following the receipt of three bits), if the next three bits of p are 111, then the FSM will output 0, since 111 is an odd number of 1s. If the next three bits after this point are 000, then the FSM will output a 1 after the third 0 is received as the third 0 here completes the most recent set of three bits "000" and the last three bits contain zero 1s (zero is, of course, an even number). Note also that the FSM should output 0 if the three bit set is incomplete. P2 (8 points): Derive a minimal state table for a Moore FSM that acts as a three-bit parity generator. For every three bits that are observed on the input b during three consecutive clock cycles, the FSM generates the parity bit p-1 if and only if the number of 1s in the three-bit sequence is even. Note that the output p may only assert after a set of three bits (six, nine, twelve, etc.) have been input. The FSM will initially have no bits and must output a 0. From this point (or any point immediately following the receipt of three bits), if the next three bits of p are 111, then the FSM will output 0, since 111 is an odd number of 1s. If the next three bits after this point are 000, then the FSM will output a 1 after the third 0 is received as the third 0 here completes the most recent set of three bits "000" and the last three bits contain zero 1s (zero is, of course, an even number). Note also that the FSM should output 0 if the three bit set is incomplete