Part $2-$ Mux and Adder $-$ Verilog and Simulation $(40$pts$)$

Using the edaplayground website, in the file design. sv instantiate two circuits

$4-$bit adder using structural verilog. You should instantiate a $1-$bit half$-$adder module, a

$1-$bit full$-$adder module using two half$-$adders, a $4-$bit full$-$adder using $41-$bit full$-$adder

module. In other words, do not just simply use $"+"$ which is behavioral

$2$:$1$ mux using ternary logic. All inputs to the mux should be $8-$bit wide.

In

testbench.sv$,$ write the code for a testbench that runs a simulation that cycles through all

inputs and displays all outputs for both circuits by using a for loop. The testbench must cover all

combinations of inputs for the adder and all select bits for the mux. For the mux drive the data

inputs to different values to show the operation of the mux. Verify your design by displaying the

inputs and outputs on the screen.

Provide screenshots of the inputs and outputs on the screen in your report. Include your verilog

files

design.sv and

testbench.sv in your ZIP file. Examples are shown below. # KERNEL: Start Verifying Adder

# KERNEL: $a+b+$cin:$0+0+0=0$

# KERNEL: $a+b+$cin:$0+0+1=1$

# KERNEL: $a+b+$cin:$0+1+0=1$

# KERNEL: $a+b+$cin:$0+1+1=2$

# KERNEL: $a+b+$cin:$0+2+0=2$

# KERNEL: $a+b+$cin:$0+2+1=3$

# KERNEL: Start Verifying Mux

# KERNEL: sel:$0,$ i$0$: $5,$ i$1$: $50,$ y: $5$

# KERNEL: sel:$0,$ i$0$: $5,$ i$1$: $51,$ y: $5$

# KERNEL: sel:$0,$ i$0$: $6,$ i$1$: $50,$ y: $6$

# KERNEL: sel:$0,$ i$0$: $6,$ i$1$: $51,$ y: $6$

# KERNEL: sel:$1,$ i$0$: $5,$ i$1$: $50,$ y: $50$

# KERNEL: sel:$1,$ i$0$: $5,$ i$1$: $51,$ y: $51$

# KERNEL: sel:$1,$ i$0$: $6,$ i$1$: $50,$ y: $50$

# KERNEL: sel:$1,$ i$0$: $6,$ i$1$: $51,$ y: $51$

Can you write the verilog code about this question and have output like this example please