PART (35 Marks) Q1: Consider the below object declarations signal sigl: std_logic_vector (7 downto: 01101101": signal sig. sig3, sig: std_lopic_vector, constant c:integer:- 80; MEC AMO_TEM_035_02 Page 1 of 11 ASIC Design (ELEC30003.2h-Fall-21-CW2 (Assignment)-OP type OP1 is (LOAD, STORE, ADD, SUB, MUL, DIVI: subtype SUB_OP IS OP1 range ADD to DIV: signal A: OPI:-ADD: signal B: SUB_OP: Signal P. Integer:13: Signal Q:integers: Signal X, Y: integer range 10 to 10, type VALUE is array (0 to 5) of integer range 25 to 75; constant NUM:VALUE= 25,35,45,55,65,75): signal RESULT: Integer Determine the output after initial execution of following codes. Justify your answer. Explain if there is any error, a. case Ais when load > Badd RESULT NUMOC when addos BC sub; RESULT NUM3) when store => Bc mul RESULT NUM[4)* when others > cdiv; RESULT NUM2V/ end case: (4 Marks) b. if NUM[4) = 70 then 75: else CC 95, endit; (3 Marks) sig2 ca sig sil2: sig 3 csigi sra-2: sig4.casteor sig (4 Marks) d. Xcp moda yoprema (4 Marks) e. What is the data type of object A? 12 Marks) c