Q1: Consider the below object declarations signal sigl: std_logic_vector (7 downto): 1101101"; signal sig2.983, sigt: std_logic_vector, constante integer: 80 MEC_AMO_TEM_035.02 Page 1 of 11 ASIC Design (ELEC20003.1-Fall-21-CW2 (Assignment)-OP type OPI IS (LOAD, STORE, ADD, SUB, MUL, DIV): subtype SUB_OP is OP1 range ADD to DIV; signal A: 0P1ADD signal B: SUB_OP, Signal P: integer-13: Signal Q:integer--5; Signal X, Y: integer range -10 to 10, type VALUE is array (0 to 5) of integer range 25 to 7S; constant NUM:VALUE:4 25, 35, 45, 55, 65, 75); signal RESULT:integer; Determine the output after initial execution of following codes. Justify your answer. Explain if there is any error a case Ais when load > Be add RESULT = NUMOC when add-> Busub RESULT NUM(3-6 when store > Bomul RESULT NUM[4C when others Bodiv RESULTNUMZ end case (4 Marks) b. if NUM[4) - 70 then cc 75 else C95 end (3 Marks) sig2