Q1: Consider the below object declarations signal sigl: std_logic_vector (7 downto Oj: 201101101" signal sig2, sie3. sgt std_logic_vector constante integer. - 30 MEC_AMO_TOM_03_02 Page 1 of 11 ASIC Design (ELEC30003,2)-Fall-21- C2 (Assignment)-OP type OPI IS (LOAD, STORE, ADD, SUB, MUL, DIVE subtype SUB_OP is OPI range AD to DIV signal A: OP1=ADD: signal B: SUB OP: Signal P: integer --13: Signal Q:integer-5 Signal X, Y integer range -30 to 10 type VALUE is array o to S) of integer range 25 to 75: constant NUM:VALUE_{25,35,45,55,65,75 signal RESULT:integer; Determine the output after initial execution of following codes. Justify your answer. Explain if there is any error a case Ais when load > Badd: RESULTCNUMOJC when add Bosube RESULT NUM) when store > Bemul RESULTNUM(4195 when others > Bodiv. RESULT - NUM(21 end case: (4 Marks) b. if NUM[4) 70 then cca 75 else (3 Marks) CC# 95: endit, c sig2 csils 2: sig 3 csiglsra 2 sig & sig or sig d. Cep mode: yce prema e. What is the data type of object A? (4 Marks) (4 Marks) (2 Marks)