Part I:

Positive edge$-$triggered flip$-$flops respond when the clock signal $q,$

A$.$ changes from $1$ to $0$

B$.$ changes from $0$ to $1$

C$.$ stays unchanged to $1$

D$.$ stays unchanged to $0$

E$.$ None

A JK flip$-$flop behaves like a T flip$-$flop when

A$.$ J and K inputs are connected together

B$.$ K is the complement of J

C$.$ J and K are both set to high $("1")$

D$.$ J and K are both set to low $("0")$

E$.$ None

For the following circuits, the level sensitive circuit is $q,$

A$.$ the gated D latch,

B$.$ the T flip$-$flop,

C$.$ the D flip$-$flop,

D$.$ None

For the following circuits, the edge$-$triggered circuit is $q,$

A$.$ the gated D latch,

B$.$ the basic SR latch,

C$.$ the D flip$-$flop,

D$.$ None

For the following circuits, the negative edge$-$triggered circuit is $q,$

a$.$

b$.$

c$.$