Please help me understand this :

MIPS Assembly Language Question

Given the following M.I.P.S code

ADDI $17, $0, 10

ADD $18, $0, $0

LOOP:

LW $8, 12($19)

ADD $18, $18, $8

ADDI $17, $17, -1

SLT $9, $0, $17

BNE $9, $0, LOOP

ADDI $18, $18, 1

SW $18, 12($19)

which was derived from this Java Code:

int loopCount = 10;

int sum = 0;

do {

sum += values[3];

loopCount--;

} while (loopCount > 0);

sum++;

values[3] = sum;

with reg assigned as follow:

$17 = loopCount

$18 = sum

$19 = top of values array

Assume we run that MIPS code on a 5-stage pipelined MIPS processor

a) Identify all data hazards and state which register causes it and between which 2 instruction it occurs.

b) for each identified data hazard above, if data forwarding is implemented, list which forwarding MUX will be used to trigger it, and what the value will be set to (e.g. FORWARDB = 1). If the data hazard will also require a stall, note it.

c) During the pipeline cycle that evaluates whether the BRANCH instruction in your code will require any data to be forwarded to it, what is in each of the following pipeline registers?

ID/EX.RegisterRs?

ID/EX.RegisterRt?

EX/MEM.RegisterRd?

MEM/WB.RegisterRd?