Please provide this Verilog, with design code and test bench please. I have a working design code and here it is below.

Design Code:

module lab3_a(input [3:0] bcdin, output reg[6:0] segs ); always @(*) begin case (bcdin) 4'b1111: segs = 7'b0000001; //0 4'b1110: segs = 7'b1001111; //1 4'b1101: segs = 7'b0010010; //2 4'b1100: segs = 7'b0000110; //3 4'b1011: segs = 7'b1001100; //4 4'b1010: segs = 7'b0100100; //5 4'b1001: segs = 7'b0100000; //6 4'b1000: segs = 7'b0001101; //7 4'b0111: segs = 7'b0000000; //8 4'b0110: segs = 7'b0000100; //9 4'b0101: segs = 7'b0001000; //A 4'b0100: segs = 7'b1100000; //b 4'b0011: segs = 7'b0110001; //C 4'b0010: segs = 7'b1000010; //d 4'b0001: segs = 7'b0110000; //E 4'b0000: segs = 7'b0111000; //F default: segs = 7'b1111111; //10: segs Lab 3 - Seven-Segment Display Counter 1. Description In this lab, you need to implement a counter that makes the seven-segment display count from hexadecimal number F to 0 and then start over from F. Figure 1 shows an example of an active- high seven-segment display with hexadecimal numbers. Note that if you use a common Anode seven-segment display, the logic in Figure 1 will be inverted with active-low seven-segment display. e 1 0 1 1 1 0 0 1 1 0 0 1 211 31 0 0 1 1 41 S1 6 71 0 1 B1 1 1 1 1 911 ALL 61 11 1 Elio 011 0 1 1 1 1 0 Figure 1. Seven-segment display with hexadecimal numbers. 1 In order to implement the counter, you will need to calculate the correct counting period for the seven-segment display based on the system clock of your implementation. For example, if your implementation runs on a 100MHz clock and you want to update the value of the seven-segment display every second, then you should wait for 100 million positive edges of the clock in Verilog to update your seven-segment display. 2. Deliverables Write a Verilog description of the seven-segment display counter. Show a demo of the seven- segment display counter that counts from F to 0, and then start from F again with a period of 1 second