PLEASE SHADE WHICH SIDE.... Using the multi$-$cycle pipeline diagram below mark up the pipeline to show the forwarding and

stalls needed to execute the following instructions on the pipelined MIPS processor. Also mark

the resources that are being used in each instruction.

add $t$0,$ $s$0,$ $s$1$

sub $t$0,$ $t$0,$ $s$2$

lw $t$1,60($$t$0)$

and $t$2,$ $t$1,$ $t$0$

add $t$1,$ $t$1,$ $t$2$