please solve this question

8. If both inputs of an S-R Latch are ZERO, what will happen when the clock goes ONE? A. An invalid state will exist No change will occur in the output C. D The output will toggle The output will reset 9When using positive edge-triggered lip-flops, the data is entered into the flip-flop on the leading edge of the clock, but the output does not change untl the trailn edge of the clock. A. True B. False 10, when the output of a NAND version ofa clocked S-R latch is Q-1 and Q' = 0, the inputs could be s-1, R-1 The Master Salve D flip-flop has an invalid state. Asequential circuit that has inputwhich can only be accepted when an enable or clockis?Nis called asynchronous True B False 11 TrueB False 12 TrueB. False 13 A D-type latch is able to change states anc "follow" the D input regardless of the level of the ENABLE (or CONTROL) input TrueB False One example of the use of a flip-lop is as a(n) A. B a stable oscillator C. binary storage register D. ransition pulse generator race IS With regard to a D latch, A follows D input when C (or EN) is ZERO B Qis opposite the D input when C (or EN) is ZERC C. follows the D input whea C (or EN) is ONE D is ONE regardless of C's (or EN's) input sa 16 When the output of a NOR version of a S-R latch is Q 1 and A S I,R-1 0, the inputs could be C S-0, R1 E. B&D FA&B 17 when ths otpul or the NAND gale irlatch iso-lando-co, the inputs could be C S-0, R 1 D S I, R- E A&C F B&D