Please type answers if possible, I have trouble reading some peoples handwriting

2, (chapter 4.3) Assume that the logic blocks needed to implement a processor's datapath have the following latencies: I-Mem Add Mux ALURegs D-Mem Sign-Extend Shift-Left-2 200ps 70ps 20ps 90ps 90ps 250ps 5ps0ps a, if the only thing we need to do in a processor is fetch consecutive instructions (Figure 4.6), what would the cycle time be? (2 point) b, consider a datapath similar to the one in Figure 4.11 but for a processor that only has one type of instruction: unconditional PC-relative branch. What would be the cycle time for this datapath? (2 points) c, Repeat part b), but this time we need to support only conditional PC-Relative branches. (2 points) d, Which kind of instructions require datapath element Shift-Left-2? (2 points) e, Assume that we only support beq and add instructions, discuss how changes in the given latency of shift-Left-2 affect the cycle time of the processor. Assume that the latencies of other resources do not change. (2 points)