PLEASE USE ARM, NOT MIPS.

3. Cache Assume we have a two-way set associative write-back cache, with 4-word blocks per cache line and 2 possible index values. Assume that the memory address is 32 bits wide and the memory is byte-addressable (a) Compute the number of address bits used for each of the following: block offset byte offset, tag, and set index. Show all calculations whenever needed (b) Calculate the total amount of memory (in bytes) required to build this cache (in- cluding both data and other necessary bits)? Show all calculations whenever needed (c) Given is a series of address references given as word addresses: 4,6, 15, 21, 7, 8, 23, 16, 13. Assume the cache in this problem is initially empty. Complete the table below. Label each reference in the list as a hit or a miss. Assume a LRU replacement policy (with a complete knowledge of the last reuse time for every cache line) Word address Block offsetSet index Tag Set entry Hit/miss 15 21 23 16 13 3. Cache Assume we have a two-way set associative write-back cache, with 4-word blocks per cache line and 2 possible index values. Assume that the memory address is 32 bits wide and the memory is byte-addressable (a) Compute the number of address bits used for each of the following: block offset byte offset, tag, and set index. Show all calculations whenever needed (b) Calculate the total amount of memory (in bytes) required to build this cache (in- cluding both data and other necessary bits)? Show all calculations whenever needed (c) Given is a series of address references given as word addresses: 4,6, 15, 21, 7, 8, 23, 16, 13. Assume the cache in this problem is initially empty. Complete the table below. Label each reference in the list as a hit or a miss. Assume a LRU replacement policy (with a complete knowledge of the last reuse time for every cache line) Word address Block offsetSet index Tag Set entry Hit/miss 15 21 23 16 13