PRELIMINARY WORK:

Consider a typical CMOS inverter for $V_{DD}=5V$ and the transistor parameters are $V_{Tn}=-V_{Tp}=0\mathrm{.}7V$ and $K_n=K_p=0\mathrm{.}45m\frac{A}{V^2}.$ Answer the following questions accordingly.

a$.$ Determine and plot the Voltage Transfer Characteristics $($VTC$)$ of $V_{\text{o}\text{u}\text{t}\text{p}\text{u}\text{t}}$ Vs$.V_{\text{i}\text{n}\text{p}\text{u}\text{t}}$ for the typical CMOS inverter.

b$.$ Determine the critical input and output voltages $($i$.$e$.V_{IL},V_{IH},V_{OL},$ and $V_{OH}).($You can find out from the simulation$)$

c$.$ Determine low and high noise margins. $($i$.$e$.N{M}_L$ and $N{M}_H).$

d$.$ Explain the effect$($s$)$ of $K_n$ and $K_p$ on $N{M}_L$ and $N{M}_H.($from the simulation$)$

Design and draw a CMOS logic circuit that realizes the function $Y\frac{?}{b}=ar(A)+(\frac{?}{\text{b}\text{a}\text{r}}(B+C)).$ Answer the following questions accordingly.

a$.$ Determine the least number of transistors to be used for this circuit. Hint: Apply De Morgan's Law.

b$.$ Specify W$/$L for all transistors in the logic function $($suppose that the transistor width sizing ratio of PMOS:NMOS is $2$:$1$ for a typical CMOS inverter.$)$

c$.$ Explain the effect$($s$)$ of connecting a capacitor to the output of the logic circuit.