Problem $1$: Following latencies are defined for a processor using multicycle operations:

$($in $ns)$

The Distribution of instructions is as follows. R$-$Type: $55\%$; Branching $10\%$; LW: $20\%$; SW $15\%$

All LW instruction are followed by an R$-$type instruction which uses the result of the LW instruction resulting

in a stall of $600.$ns in the pipelining. Situation.

For a non$-$pipelined sequential operation, determine

$($a$)$ the average latency

$($b$)$ the average thruput

For pipelined operation, determine

$($c$)$ the average latency

$($d$)$ the average thruput