Problem $2.(20$ points$)$ Basic cache

Consider a memory system composed of a single cache and DRAM. The parameters of the memory system are given below:

$-$ Memory address: $16-$bit

$-$ Cache line size: $16$ bytes

$-$ Cache capacity: $64$ bytes

$-$ Set$-$associativity: $2$

$-$ Replacement policy: LRU

$-$ Write$-$back, write$-$allocate policy

$-$ Cache access latency: $4$ cycles

$-$ DRAM access latency: $100$ cycles

A$.(2$ points$)$ How many bits are required for a tag for a cache line in this cache?

B$.(3$ points$)$ What is the total storage overhead per cache line other than the tag bits if cache coherence is not supported $($i$.$e$.,$ the cache is for a uniprocessor$).$ Examine the design parameters carefully one by one and make sure that all the features are supported.

C$.(3$ points$)$ If MESI coherence protocol support is added to the cache, what is the minimal amount of additional storage overhead per cache line required? Ignore the transient states for this problem.