Problem 2 Consider the following DLX code. Assume that initial values of all registers and memory are zero Assume there is no forwarding hardware.Assume the architecture shown at the end of this problem (registers are written in the first half of3 the cycle and read in the second half of the cycle and that branches are resolved during decode) No ddi 1.ro odd Fill in the pipeline timing diagram a the bottom showing the execution of the DLX code given below. Use the following codes:F fetch. D decode, X execute. M memory access, W write hack, s stall. Tbe first instruction is filled in for you. Show oaly the first ten instructions executed. ['The numbers above each column are provided to help you count cycles -ty instruction 0 i 2 4 S 6 T S 9-10 2 is i4 is 6-17 is 1, 20 21 18 19 (1) FDX M W