Problem 2c (30 points): Suppose we have a static 2-issue MIPS processor, as in Fig. 4.69. Show timing for one unrolled iteration of the loop from Problem 2b, using a table similar to Fig. 4.70. You should change the order of the instructions to optimize the performance. Use these assumptions for the hardware: Unit 1 for ALU/branch instructions, Unit 2 for lw/sw If an arithmetic instruction executes in cycle 1, its result can be used in cycle 2 by a lw, sw or arith instruction its result can be used in cycle 3 by a branch If a lw executes in cycle 1, its result can be used in cycle 3 by lw, sw or arith instructioin its result can be used in cycle 4 by a branch Problem 2c (30 points): Suppose we have a static 2-issue MIPS processor, as in Fig. 4.69. Show timing for one unrolled iteration of the loop from Problem 2b, using a table similar to Fig. 4.70. You should change the order of the instructions to optimize the performance. Use these assumptions for the hardware: Unit 1 for ALU/branch instructions, Unit 2 for lw/sw If an arithmetic instruction executes in cycle 1, its result can be used in cycle 2 by a lw, sw or arith instruction its result can be used in cycle 3 by a branch If a lw executes in cycle 1, its result can be used in cycle 3 by lw, sw or arith instructioin its result can be used in cycle 4 by a branch