Program: Altera, Verilog

The Altera parameterized modules offer a powerful method for building datapaths. Use two LPM MULT modules to implement the following operation: Y-Bx where B is a 4 bit number representing a fixed point number xxxx.0 that will range from 0.0 to 15.0. All possible 4-bit codes are valid for input B. The input a is a 4 bit fixed point number in the 0xxxx format. xi will range from 0.0000 to 0.9375. In binary, this range wll be 0000 to 1111 (note that there are 4 binary digits assumed to be in the format 0.xxxx) The multiplication used for computing x? will result in a value of the format O.xxxxxxxx which will need to then be multiplied with B which is initially of the form xxxx.0, the final product will be of the form xxxxxxxx.xxxxxxxxxxxxxxxx. You may use Verilog modules to perform padding of the operands before they are supplied to the LPM MULT inputs similar to the example schematic supplied to you in Lab 2. You are to implement this function using two LPM MULT you find that you need other functionality, then you may use either Verilog or schematic capture to implement the functionality. Your design should be named mult3 parameterized modules. If The Altera parameterized modules offer a powerful method for building datapaths. Use two LPM MULT modules to implement the following operation: Y-Bx where B is a 4 bit number representing a fixed point number xxxx.0 that will range from 0.0 to 15.0. All possible 4-bit codes are valid for input B. The input a is a 4 bit fixed point number in the 0xxxx format. xi will range from 0.0000 to 0.9375. In binary, this range wll be 0000 to 1111 (note that there are 4 binary digits assumed to be in the format 0.xxxx) The multiplication used for computing x? will result in a value of the format O.xxxxxxxx which will need to then be multiplied with B which is initially of the form xxxx.0, the final product will be of the form xxxxxxxx.xxxxxxxxxxxxxxxx. You may use Verilog modules to perform padding of the operands before they are supplied to the LPM MULT inputs similar to the example schematic supplied to you in Lab 2. You are to implement this function using two LPM MULT you find that you need other functionality, then you may use either Verilog or schematic capture to implement the functionality. Your design should be named mult3 parameterized modules. If