Q$1)$ Assume a single$-$cycle processor with the following stages and the time per stage:

Stage IF ID EX MEM WB

Time $($ns$)42395$

For an ideal pipleined architecture, what is the maximum speedup?

Q$2)$ Assume a single$-$cycle processor with the following stages and the time per stage:

Stage IF ID EX MEM WB

Time $($ns$)510969$

For a pipleined architecture what is the clock time $($in ns$)?$

Q$3)$ Assume a single$-$cycle processor with the following stages and the time per stage:

Stage IF ID EX MEM WB

Time $($ns$)92855$

For a pipleined architecture what is the speedup when running $32$ instructions?