Q$1.$ We begin with a computer implemented in single$-$cycle implementation. When the stages are

split by functionality, the stages do not require exactly the same amount of time. The original

machine had a clock cycle time of $16ns.$ After the stages were split, the measured times were IF$,$

$3\mathrm{.}5ns$; ID$,2\mathrm{.}0ns$; EX$,3\mathrm{.}0ns$; MEM, $5\mathrm{.}0ns$; and WB$,2\mathrm{.}5ns.$ The pipeline register delay is $0\mathrm{.}3ns.$

a$.5pt$ What is the clock cycle time of the $5-$stage pipelined machine?

b$.5pt$ If there is a stall every eight instructions, what is the CPI of the new machine?

c$.[5$ pt$]$ What is the speedup of the pipelined machine $($with the assumption of pipeline stalls

in Q$1.$b$)$ over the single$-$cycle machine?

d$.[5$ pt$]$ If the pipelined machine had an infinite number of stages and there is no pipeline

stall, what would its speedup be over the single$-$cycle machine?