Q$2(25$ pts$).$ Counter$-$like circuit. Design a counter$-$like sequential circuit using a Moore$-$type finite state machine $($FSM$)$ with D flip$-$flops. The circuit has three inputs: CLK$,$ RESET, and En$.$

The circuit counts as $\backslash (6,2,4,0,6,2,4,0\backslash )$ and so on as when $\backslash ($ E n$=1\backslash ).$ When En$=0,$ the circuit pauses counting. En is a synchronous input. The RESET is asynchronous, not synchronized with the CLOCK signal. If RESET signal is low, the counter resets to $0.$

Requirements: Please provide the bubble diagram, state table, Karnaugh maps $($or truth tables$),$ logic function for the next states and outputs, and schematic for the circuit.