Q$2.8$pts$,$ CLO$5)$ If the ratio between the size of pmos the transistor and the size of nmos transistor at cmos inverter were $3/2.$ Answer the following questions:

The size of pMOS transistors at NAND gate $3-$input is: a$.1$ b$.2$ c$.3$ d$.4$ e$.5$ f$.6$ g$.7$ i$.9$

The size of nMOS transistors at NAND gate $3-$input is: a$.1$ b$.2$ c$.3$ d$.4$ e$.5$ f$.6$ g$.7$ i$.9$

Total load capacitor in this case should be: a$.10$C b$.12$C c$.15$C d$.20$C e$.25$C f$.30$C i$.35$C

Input gate capacitor in this case should be: a$.10$C b$.12$C c$.15$C d$.20$C e$.25$C f$.30$C i$.9$C

The size of pMOS transistors at NOR gate $3-$input is: a$.1$ b$.2$ c$.3$ d$.4$ e$.5$ f$.6$ g$.7$ i$.9$

The size of nMOS transistors at NOR gate $3-$input is: a$.1$ b$.2$ c$.3$ d$.4$ e$.5$ f$.6$ g$.7$ i$.9$

Total load capacitor in this case should be: a$.10$C b$.12$C c$.15$C d$.20$C e$.25$C f$.30$C i$.15$C

Input gate capacitor in this case should be: a$.10$C b$.12$C c$.15$C d$.20$C e$.25$C f$.11$C i$.9$C

q$2)$ if r$=2$k om c $=100$pF calculte the rise time and fall time in the $2$ input nand gate